1. Field of the Invention
This invention relates to electronic circuits and, more particularly, to circuits for multiplexing signals from clock or data sources.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many electronic systems include one or more synchronous components that rely on receiving related signals at substantially the same time to maintain proper operating characteristics of the electronic system. A computer system is one example of a synchronous system that may include a multitude of interrelated system components, each designed to perform a particular operation in response to a clock signal. In some cases, data transfer between system components may be synchronized by one or more clock signals originating from a common source. The system components may receive the clock signals through a clock network, which may include clock generation and distribution circuits.
In some cases, clock generation may be accomplished by manipulating the output of a source, such as a crystal oscillator, to generate a plurality of clock signals in accordance with the needs of the various components within the computer system. The generated clock signals may then be fanned out to the system components via a clock distribution network. In an ideal situation, the generated clock signals may be received by each of the system components at substantially the same time. In practice, however, timing delays and uncertainties of clock signal generation and distribution may cause one or more system components to receive clock signals at slightly different instances. In some cases, even the smallest variation in the arrival of a clock signal transition relative to a data signal transition may significantly impact system performance and/or reliability. For this reason, good clock distribution is very important to the overall performance and reliability of electronic systems. Unwanted clock skew and jitter are two phenomena that may result from poor clock distribution, thus causing problems in the design and operation of the electronic systems.
As used herein, the term “skew” may be described as a variation in the arrival times of two related signals, which are specified to arrive at the same time. For example, “clock skew” may occur when an active “transition” or “edge” of the clock signal “lags” (i.e., arrives sometime after) or “leads” (i.e., arrives sometime before) the data signal transition(s) received by a system component. Clock skew may be introduced into a clock network through load mismatches, routing parasitics (i.e., interlayer dielectric thickness, interconnect thickness and channel length mismatches), and/or variations in temperature, voltage, and process (i.e., trace conductor length, width, and composition mismatches, capacitive loading, etc.).
Unfortunately, clock skew may adversely affect the timing margins of one or more components within a synchronous system. For example, it is often necessary to properly align the clock signal to the data being sampled at the input latches of a system component to achieve synchronous operation. Such alignment may ensure that the data transition occurs at the proper moment between the edges or active transitions of the clock signal. Synchronous systems, therefore, generally rely on data transitioning and remaining stable from a time, which occurs at least a “setup time” before the clock transition, until at least a “hold time” after the clock transition. Most synchronous system components have stringent setup and hold timing requirements, which are typically specified by a manufacturer of the system component.
As operating speeds increase, the setup and hold timing margins between active transitions of the clock and data signals are reduced, thereby decreasing the window within which a data transition can be successfully latched by a clock transition. For example, edge-sensitive flip-flops may be used for sampling data signals received by a system component. In such an example, a flip-flop may successfully latch a data signal if the data signal is stable during the critical setup and hold periods on either side of the clock transition. However, if clock skew occurs, it may shift the clock transition sufficiently in time to cause a bit error when the data is sampled. As described herein, a “bit error” is a sampling error that occurs when a data signal is incorrectly sampled by a clock transition.
Jitter, on the other hand, generally results from time-varying components of noise sources, and is often defined as the cycle-to-cycle variation in the threshold crossings of a data signal. In other words, jitter may occur in data samples taken near, but not exactly at, the desired sample locations of an individual data signal, such that a sample is temporally displaced by an unknown, though usually small interval (e.g., an interval substantially less than or equal to one clock cycle). Like clock skew, jitter may cause the data signal to be shifted sufficiently in time to produce a bit error when the data signal is incorrectly sampled by the clock signal.
Techniques have been developed to minimize the effects of timing delays, such as clock skew and jitter, which degrade the performance and reliability of synchronous systems. However, most currently used techniques cannot guarantee that a data signal transition will occur at the critical moment between clock signal edges in all conditions. For example, some techniques utilize phase lock loops (PLLs) or delay-locked loops (DLLs) for adding a somewhat variable, though highly consistent amount of delay to a clock path. The added delay may be used to adjust the active edge of a clock signal before it is used for sampling a data signal. As such, a PLL or DLL device could be used to reduce clock skew by adjusting the timing of the clock signal, so that it occurs within the data setup and hold time requirements of a system component. However, the current techniques are not without some disadvantages.
In some cases, more than one PLL or DLL device may be included within a clock network for adjusting the timing of the clock path. Multiple PLL/DLL devices enable the system to multiplex clock signals from different PLL/DLLs. For example, a multiplexer circuit may be included for selectively applying one of the PLL/DLL output signals to the clock path. However, conventional multiplexer designs add crosstalk and power supply noise to the clock path when multiplexing signals (i.e., choosing between more than one signal) from the PLL/DLLs.
The addition of crosstalk and power supply noise increases the amount of jitter on the clock path, and therefore, is very undesirable in clock networks. In some cases, the amount of jitter added to the clock path may cause a bit error when the generated clock signal is used for sampling data. Therefore, a need remains for an improved clock network that does not suffer from crosstalk or supply noise injection. Such a clock network may experience significantly less jitter than conventional networks, thereby improving the overall timing of an electronic device employing the clock network.